AlphaChips

Initial Design Review Meeting

     1. When:
         - After the project is approved by project review committee
    2. Major Review Items:
         1) Decide the Design Methodology: TDD, Physical Synthesis, Trial Layout
         2) Define the Role & Business Model: Level 1.0~3.0
         3) Review the Design schedule
         4) Pre-Review the Test Related Issues (ex : Analog Test Board )
         5) Pre-Review the QA Related Issues (ex: Qual Board)
    3. Attendees:
         - End-Customer, Marketing, Front-end Engineer (AlphaChips), IP Engineer
    4. Output :
         - Initial Design Review Sheet & the Meeting Minutes

Feasibility Study

     1. When:
         - Initial Design Step
    2. Major Review Items:
         1) Building Up the Basic Environment: D/K Release, Special Cell, GCM Code
         2) Library Selection Guide & Design Specification Review
              - Generic or Low Power Process/Commercial or Industrial
         3) Power Management System Review
              - Low Power Design (Power Synthesis, Clock Scheme, Voltage Review)
         4) Pin File Review
              - Power Pad Calculation & Power Consumption Review
              - Application Specific I/O ( I/O Specifications Decision)
         5) IP Related Issue Review
              - Specification Review for New A-Core, D-Core, I/O IP and Review the Design Kit
         6) Cost Effective Activities
              - Test Methodology Review (Test Time, Tester Selection Guide)
              - High Density SRAM (Repairable Analysis) & Yield Improvement Review
         7) Log File Review (if there are some design bug)
         8) PKG Related
              - Power Consumption Estimation & Package Guide
              - Special Approval by PKG Team in BGA Package Cases
              - Special Marking Review

Front-end Design Service

      1. When:
          1) Level 1.0 Interface: During Block Level RTL Coding by Designer
          2) Level 2.0 Interface: 2 weeks prior to before Gate Level Netlist Freeze
      2. Design Service Items:

Design Service	Items	Description
Logic Synthesis	Linting	RTL Code Check & Review
	Code Coverage	Coverage Analysis of RTL Code
	Logic Synthesis	RTL-to-Gate Synthesis
Physical Synthesis	Physical Synthesis	Physical Optimization by Using PC
Design for Test	BIST/BIRA	SRAM BIST DK & BIRA Generation
	Scan Stitching	Building Scan Chain, Scan Logic STA
	Scan ATPG	Scan Design Rule Check., ATPG
	JTAG Design	Insertion, Compliance Check, BSR
Timing Closure	CWLM	Customer Wire Load Model
	Reoptimization	Post-Optimization by Using PDEP
	MTTV Repair	MTTV Repairing
Design Verification	Timing Simulation	Gate Level Logic Simulation
	STA	STA for Each Design Step
	Equivalence Check	Gate-to-Gate Equivalence Check
Layout Interface	Floorplan Interface	Floorplan Inform for Optimum P&R
	CTS Interface	CTS Point Review & Define Spec
	SDF/Netlist Interface	P&R Netlist, SDF Generation
Test Vector	Test Backannotation	Test Vector Backannotation

Pre-Layout Review Meeting

     1. When:
         - 2 days prior to before Layout Start
     2. Major Review Items:
         1) Pre-Layout Design Review Sheet Review
         2) DB Check
              ① Netlist/Cubic Output Files ( *.adv_rpt, *.adv_err, *.adv_warn,*.sa_pin)
              ② Check the Layout Information
                    - Block Diagram
                    - Critical Path/Hard-macro Information
                    - Clock Network Information & CTS Specification: CTS Ignore Point & CTS Net
                    - JTAG Boundary SCAN Information (Optional)
         3) Check the Floor Plan Information for P&R (Logical → Physical Structure)
         4) Check the Constraint Script for STA (Include Timing Exception Path)
     3. Output:
          - Pre-Layout Design Review Sheet & the Meeting Minutes

P&R, Timing Closure

1. Major Design Service Items:

Items	Description
DB Preparation	Hard-macro Core Phantom,GDS & CLF File
Floorplan	Initial Layout: Hard-macro Floorplan
CTS	Clock Tree Synthesis According to CTS Specifications
Place and Routing	P&R by Using Apollo/Astro/Blast-Fusion Tool
RC Extraction	Cap File Extraction after Routing
ECO	Engineering Change Order for Timing Closure
TDL	Timing Driven Layout by Saturn (Optional)
MTTV Optimization	MTTV Optimization by Saturn

    2. Front-End Engineering Support :
        1) Give feedback the correct CTS information to back-end engineer
        2) Boundary Condition File Generation for TDL
        3) SDF Generation & Cubic Repair & STA Execution & Equivalence Check
        4) BSR List Generation for JTAG Design

Post-Design Review Meeting

     1. When:
         - Before PG
     2. Major Review Items:
         1) Review the Post Design Review Sheet
         2) Review the Test Related Issues (Test Method & Analog Test) & QA Related Issues
         3) Fix the ER schedule & Issue the T/S
         4) Register Device, Test, Assembly Specification at Leaders.
         5) Secure Netlist, Cubic Output File, Function Test Pattern Set, Nand Test Pattern Set
         6) Fault Coverage Check
         7) Secure the Post-Layout Approval Sheet
     3. Output:
         - Post Design Review Sheet, Design Review Meeting Minutes

Verification & PG

1. Major Design Service Items:

Items	Description	Remarks
Multi-Power LVS	LVS Check by Using Multi-Power Netlist from Cubic
DRC	Physical Design Rule Check
Antenna Check	Antenna Check & Repair if there is an error	From STD110
Double VIA	Double VIA Generation by Using DUO_MAN Utility	From STD90
OPC	Optical Proximity Generation	From STD110
Base Layer PG	Base Layer (before Metal Layer) E-Beam File
Mask Tooling	Apply Mask Tooling
Reticle Frame	Apply Reticle Frame
Option Layer PG Out	Option Layer (after Metal Layer) E-beam Generation