|
Model
|
Division
|
Activities
|
|
RTL Sign-Off
|
Front-end |
1. RTL Code & Constraints
Analysis
2. Logic Synthesis
3. Equivalence Check (RTL to Netlist)
4. Netlist Check
5. LTL (Initial Floorplan / CWLM / Reoptimization)
6. DFT (SCAN / ATPG / JTAG / BIST) Insertion
7. Static Timing Analysis (Function Mode / SCAN Mode)
8. Test Logic Timing Analysis
9. Layout Interface (Floorplan / CTS Review)
10. Analog Floorplan Review
11. ESD Review
12. Package Review & Bonding Simulation
13. Clock Optimization
14. Equivalence Check (Original Netlist to CTS Netlist)
15. MTTV Fix
16. Multi Power LVS Netlist Generation
17. Test Vector Generation and Backannotation
18. Design Review Meeting
19. Issue Traveller Sheet
20. Register Device / Bonding / Test
Specifications
21. Support Test Failure Analysis
22. Support Mass Production
23. Support Front-end Engineering Inquiry |
| Back-end |
1. TDL or Non-TDL Auto P&R
2. Verification
3. PG |
