|
Model
|
구 분
|
지원 항목
|
|
RTL Sign-Off
|
Front-end
|
1. RTL Code & Constraint
입수 및 분석
2. Logic Synthesis
3. Equivalence Check (RTL to Netlist)
4. Netlist 검토
5. LTL (Initial Floorplan / CWLM / Reoptimization)
6. DFT (SCAN / ATPG / JTAG / BIST) Insertion
7. Static Timing Analysis (Function Mode
/ SCAN Mode)
8. Test Logic Timing Analysis
9. Layout Interface ( Floorplan / CTS 검토)
10. Analog Floorplan 검토
11. ESD 검토
12. Package & Bonding 검토
13. Clock Optimization
14. Equivalence Check (Original Netlist vs
CTS Netlist)
15. MTTV Fix
16. Multi Power LVS Netlist 제작
17. Test Vector Generation and Backannotation
18. Design Review Meeting
19. Traveller Sheet 발행
20. 제품 규격 / 조립 규격 / 검사 규격 등록
21. Test Failure Analysis 지원
22. 양산 지원
23. Front-end Engineering Inquiry 지원
|
|
Back-end
|
1. TDL or Non-TDL
Auto P&R
2. Verification
3. PG |
